1. Field of the Invention
This invention relates generally to the field of memory logic devices and more specifically to a simultaneous read or simultaneous write (SRSW) array. More particularly, the present invention relates to memory array having a first and second port for reading and writing to the array. Still more particularly, the present invention relates to memory array that may have a plurality of read ports and a plurality of write ports.
2. Description of the Background Art
Memory devices are well known in the semiconductor industry. In particular, memory cores for integrated circuits continue to be improved. Because of the proliferation and popularity of application specific integrated circuits (ASIC), there is a need for improved designs for memory cores or arrays. New memory cores are needed because of the every decreasing size requirements for ASICs. For example, new uses for ASICs such as cellular telephones, portable computers, and hand held devices require new memory cores that require less circuit area to implement. Even despite the increases in transistor density provided by new semiconductor process technologies, there continues to be a need for memory cores or array designs that require less area.
Yet another reason for requiring smaller memory cores or arrays is that they consume less power. Especially, in the applications noted above such as cellular telephones, portable computers, and hand held devices, the power available is severely limited. Since smaller memory cores consume less power, the reduced power requirements also drive the need for smaller and more energy efficient memory cores. Thus, there is a need for memory cores that consume less power.
Still another reason for memory cell arrays of smaller size is to increase the memory capacity in the same area. Since ASICs are more complicated and perform many more functions than in the past, the memory cell arrays must be larger in size, yet fit in the same area or less. Furthermore, the area of the ASIC dedicated to other components using or accessing the memory cell arrays has increased because of their increased complexity and computing abilities. Therefore, more of the area is dedicated to the portion of the ASIC other than memory. Thus, there is a need for a memory cell that is smaller in size.
Finally, another shortcoming of the prior art memory cells is there ability to be reduced in size as the semiconductor process technologies are reduced in size. More particularly, one problem encountered as the process technologies are reduced to smaller and smaller dimension is that the increased noise and cross talk between the signal lines used to read the memory cells. Thus, there is also a need for a memory cell design that reduces the amount of noise that is transmitted between signal lines used for the memory cell.
Therefore, there is a need for memory cell arrays that are smaller in size, consume less power, and reduce electrical interference.